Chris Spear, "SystemVerilog for Verification: A Guide to Learning the Testbench Language Features"

Chris Spear, "SystemVerilog for Verification: A Guide to Learning the Testbench Language Features"
Publisher: Springer | ISBN: 0387270361 | edition 2007 | PDF | 326 pages | 1,4 mb

SystemVerilog for Verification teaches the reader how to use the power of the new SystemVerilog testbench constructs plus methodology without requiring in-depth knowledge of Object Oriented Programming or Constrained Random Testing.

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